The present invention relates to a flat panel display device employing a flat display panel such as an LCD (Liquid Crystal Display), a plasma display, an EL (Electronic Luminescence) display and an FED (Field Emission Display).
A TFT (Thin Film Transistor) color LCD panel is known as a typical flat display panel used as a display for computers or the like. In this TFT color LCD panel, display data for one display line are input from a display controller to a plurality of source drivers and then supplied therefrom to all source electrode lines at once, thereby displaying the data. The display data are supplied in sequence to the source drivers from the left to the right.
This data input method in which display data are supplied first to the leftmost source driver, is applied not only when data is displayed on the entire liquid crystal display section but also when data is displayed on part of the display section. Therefore, as shown in FIG. 1, even when data is displayed on a liquid crystal display section 500 at a resolution lower than the highest resolution, the data has to be transmitted from a display controller to the entire liquid crystal display section 501 (all dots including those not used for display). Thus, the display controller necessitates operating in timing necessary for display the data on the entire display section even though the data is displayed within a smaller display area 502 than the entire display section.
FIG. 2 illustrates the constitution of a prior art TFT panel unit.
In FIG. 2, input data of respective source drivers are digital signals of R, G and B, while output data thereof are analog signals of R, G and B. When each source driver receives a signal Spi, which indicates the start of data input, from a driver controller 513, it starts to supply the input data to a shift register for each of clock signals Ck. When the source driver receives a data output signal Ls, it outputs data to the shift register.
When the source drivers other than the final one input data to their own shift registers, they output a signal Spo indicative of the end of data input. The output signal Spo of a source driver other than the final one corresponds to an input signal Spi of the next source driver.
When a gate driver receives the signal Spi, it starts to apply a voltage (in sequence from the first line) to each of display lines of a liquid crystal display section in response to each scan signal Cls. All transistors of one line to which the voltage is applied are turned on.
Each of the gate drivers other than the final one outputs a signal Spo when it applies a voltage to its own last display line. The output signal Spo of the gate driver corresponds to an input signal Spi of the next gate driver.
FIG. 3 illustrates the internal structure of each source driver of the prior art TFT panel unit.
When a count circuit 601 receives a signal Spi, it outputs a signal CK' whenever its subsequent signal CK rises (or falls). The count circuit 601 counts the rise (or fall) of the signal CK. If the signal CK is input by the same number as that of shift registers, the circuit 601 stops outputting the signal CK' and outputs signal Spo.
When a data latch circuit 602 receives a signal CK', it latches signal DATA between high and low and continues to output the latched data as "DATA'" until the next signal CK' is input.
The shift register 603 has a plurality of registers (data storage sections). For example, when eight source drivers are employed in 1024.times.768 panels, the number of registers of the shift register in one source driver is 1024/8=128. Upon receiving the signal CK', the shift register 603 shifts stored data to its left register and, in this case, DATA' in the left-most register is deleted and new DATA' is stored in the rightmost register.
A voltage selection and application circuit 604 receives a signal Ls and applies one of voltages V0 to V7 to the lines corresponding to the data stored in the plural registers of the shift register 603.
FIGS. 4 to 6 show three cases of display operation timing of the prior art TFT panel.
In the case of FIG. 4, data is displayed at XGA resolution (1024.times.768 dots) on a panel having XGA resolution of 1024.times.768 dots. Eight source drivers are employed and correspond to those of FIG. 2 to which SD1 to SD8 are assigned in sequence from the left.
In FIG. 4, vertical sync signal Vsync, horizontal sync signal Hsync, display data DATA, and shift clock SHFCLK by which transfer timing of display data DATA is represented in unit of dots, are output signals of a display controller (alongside the computer body). The mesh portions indicate variations in signal levels H and L. SD1 INPUT to SD8 INPUT are input signals (input DATA) of the eight source drivers. In FIG. 4, A denotes timing in which signal Spi is input to the source driver DS1, B shows timing in which signal Spo is output from the source driver SD1 and signal Spi is input to the source driver SD2, and C indicates timing in which signal Ls is input to the source drivers SD1 to SD8. As described above, in the prior art panel, a plurality of source drivers do not receive data at the same time.
In the case of FIG. 5, data is displayed at VGA resolution (640.times.480 dots) on a panel having XGA resolution of 1024.times.768 dots. Vsync, Hsync, DATA and SHFCLK are output signals of the display controller, and the operation timing is the same as that of FIG. 4. The black portions of DATA represent timing in which the display controller outputs specific color data (e.g., black data which shows that R, G and B signals are all "0."). The black portions of SD1 INPUT to SD8 INPUT represent timing in which the specific color data is input to the shift register. More specifically, specific color data of 128 dots is input to the left-most and rightmost source drivers SD1 and SD8. Of data of 128 dots input to the source driver SD2, data of left-handed 64 dots is specific color data. Of data of 128 dots input to the source driver SD7, data of right-handed 64 dots is also specific color data.
In FIG. 6, data is displayed at VGA resolution (640.times.480 dots) on a panel having VGA resolution of 640.times.480 dots. Five source drivers are employed and correspond to those of FIG. 2 to which SD1 to SD5 are assigned in sequence from the left. Vsync, Hsync, DATA and SHFCLK are output signals of the display controller, and SD1 INPUT to SD5 INPUT are input data of the five source drivers SD1 to SD5.
Comparing FIGS. 4 and 5, it is seen that the frequencies of SHFCLK and Hsync are decreased, for the resolution of the panel is low.
As described above, conventionally, even when part of an LCD section is used for displaying data, the operation speed and timing of the display controller are the same as those when the whole LCD section is used therefor and, in the remaining part of the LCD not used for displaying data, specific color data has to be sent to an LCD panel from the display controller. When part of the LCD panel is employed, the display controller has to operate at the same speed as that when the entire LCD panel is used. For this reason, in the prior art, the maximum number of colors, which can be displayed on part of the LCD panel, is restricted. For example, if the following restrictions are placed on the display controller, data of the hatched portions of FIG. 7 cannot be displayed.
Memory capacity for displaying data: 2 MB or less Transfer Rate: 2 MB or less per 1/60 seconds.
If a prior art 640.times.480 panel is connected to the display controller, 16M colors can be displayed to the maximum. If, however, data is displayed by 640.times.480 dots using part of the prior art 1024.times.768 panel, the maximum number of colors which can be displayed will be 64K and is smaller than that when the 640.times.480 panel is used.
Consequently, in the prior art 1024.times.768 panel, 16M colors cannot be displayed by 800.times.600 dots or 640.times.480 dots.